JEDEC standard 1.5V (1.425V ~1.575V) Power Supply
•
VDDQ = 1.5V (1.425V ~ 1.575V)
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933MHz fCK for 1866Mb/sec/pin
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8 independent internal bank
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Programmable CAS Latency: 13, 11, 10, 9, 8, 7, 6
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Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
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8-bit pre-fetch
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Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write [either on the fly using A12 or
MRS]
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Bi-directional Differential Data Strobe
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Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
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On Die Termination using ODT pin
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Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE
< 95°C
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Asynchronous Reset
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Height 1.291” (32.80mm) w/heatsink, double sided
component
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